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- , commercial at 0101 65 0x41 a 0102 66 0x42 b 0103 67 0x43 c 0104 68 0x44 d 0105 69 0x45 e 0106 70 0x46 f 0107 71 0x47 g 0110 72 0x48 h 0111 73 0x49 i 0112 74 0x4a j 0113 75 0x4b k 0114 76 0x4c l 0115 77 0x4d m 0116 78 0x4e n 0117 79 0x4f o 0120 80 0x50 p 0121 81 0x51 q 0122 82 0x52 r 0123 83 0x53 s 0124 84 0x54 t 0125 85 0x55 u 0126 86 0x56 v 0127 87 0x57 w 0130 88 0x58 x 0131 89 0x59 y 0132 90 0x5a z 0133 91 0x5b [, open square bracket 0134 92 0x5c \, backslash 0135 93 0x5d ], close square bracket 0136 94 0x5e ^, caret 0137 95 0x5f _, underscore 0140 96 0x60 `, back quote 0141 97 0x61 a 0142 98 0x62 b 0143 99 0x63 c 0144 100 0x64 d 0145 101 0x65 e 0146 102 0x66 f 0147 103 0x67 g 0150 104 0x68 h 0151 105 0x69 i 0152 106 0x6a j 0153 107 0x6b k 0154 108 0x6c l 0155 109 0x6d m 0156 110 0x6e n 0157 111 0x6f o 0160 112 0x70 p 0161 113 0x71 q 0162 114 0x72 r 0163 115 0x73 s 0164 116 0x74 t 0165 117 0x75 u 0166 118 0x76 v 0167 119 0x77 w 0170 120 0x78 x 0171 121 0x79 y 0172 122 0x7a z 0173 123 0x7b {, open curly bracket 0174 124 0x7c |, vertical bar 0175 125 0x7d }, close curly bracket 0176 126 0x7e ~, tilde 0177 127 0x7f delete see nul, soh, stx, etx, etx, eot, enq, ack, bel, bs, ht, line feed, vt, ff, cr, so, si, dle, xon, dc1, dc2, dc3, dc4, nak, syn, etb, can, em, sub, esc, fs, gs, rs, us, space, exclamation mark, double quote, hash, dollar, percent, ampersand, quote, open parenthesis, close parenthesis, asterisk, plus, comma, minus, full stop, oblique stroke, colon, semicolon, less than, equals, greater than, question mark, commercial at, open square bracket, backslash, close square bracket, caret, underscore, back quote, open curly bracket, vertical bar, close curly bracket, tilde, delete. last updated: 1996-06-24
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Từ điển Máy Tính - Foldoc Dictionary
pipeline 
pipeline (architecture) A sequence of functional units ("stages") which performs a task in several steps, like an assembly line in a factory. Each functional unit takes inputs and produces outputs which are stored in its output buffer. One stage's output buffer is the next stage's input buffer. This arrangement allows all the stages to work in parallel thus giving greater throughput than if each input had to pass through the whole pipeline before the next input could enter. The costs are greater latency and complexity due to the need to synchronise the stages in some way so that different inputs do not interfere. The pipeline will only work at full efficiency if it can be filled and emptied at the same rate that it can process. Pipelines may be synchronous or asynchronous. A synchronous pipeline has a master clock and each stage must complete its work within one cycle. The minimum clock period is thus determined by the slowest stage. An asynchronous pipeline requires handshaking between stages so that a new output is not written to the interstage buffer before the previous one has been used. Many CPUs are arranged as one or more pipelines, with different stages performing tasks such as fetch instruction, decode instruction, fetch arguments, arithmetic operations, store results. For maximum performance, these rely on a continuous stream of instructions fetched from sequential locations in memory. Pipelining is often combined with instruction prefetch in an attempt to keep the pipeline busy. When a branch is taken, the contents of early stages will contain instructions from locations after the branch which should not be executed. The pipeline then has to be flushed and reloaded. This is known as a pipeline break. Last updated: 1996-10-13
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